(1) Field of the Invention
The present invention relates generally to semiconductor integrated circuit technology and more particularly to split gate memory cells used in flash EPROMs (Electrically Erasable Programmable Read Only Memory).
(2) Description of Prior Art
A basic operation in split gate flash EPROMs is the programming operation. In the programming operation charge is introduced into the floating gate of the split gate flash memory cell. Traditionally programming by source side injection, the introduction of charge into the floating gate, is accomplished in two steps. In the first step, channel electrons are heated by the electric field parallel to the channel so that when they are opposite the floating gate there is a significant number of electrons with increased energy. Secondly, the electrons must overcome the gate oxide potential barrier to pass into the floating gate. The higher the electron energy and the electric field normal to the channel the easier it is to penetrate the barrier and the more efficient the charging of the floating gate. This two step process is shown in FIG. 1. Electrons in the channel at point 1, under selected gate 2, are accelerated in passing to point 3, under the floating gate 4, by a field E1x, which is determined by the potential difference, V31, between points 3 and 1. The voltage of the selected gate, which should be low, determines the potential at point 1. The voltage applied to the top gate, 6, determines the voltage of the floating gate to which it is coupled. The voltage of the floating gate, which should be high, in turn determines the voltage at point 3. The larger is V31 the larger is the hot electron generation rate, the rate at which electrons gain energy. To enter the floating gate, such as by going from point 3 to point 5, channel electrons need to traverse the potential barrier posed by the gate oxide, 14. The rate at which electrons traverse the gate oxide barrier depends on the electron energy, the direction of the electron""s motion relative to the barrier, and the electric field, E2y, across the barrier. The electric field E2y is determined by the voltage of the floating gate, which is determined by the voltage applied to the top gate. Higher electron energy, motion more normal to the barrier and higher fields across the barrier are favorable for barrier penetration. E1x, which is perpendicular to E2y, determines electron energy and thus these two fields act independently. Furthermore the action of E1x is to accelerate electrons along the direction of the channel, which is in a direction parallel to the barrier or the least efficient direction. Only electrons that scatter and who""s scattering angle is near a right angle, so that after scattering they are moving normal to the barrier, will have a reasonable probability of traversing the barrier. To overcome these distractions in the efficiency of charging the floating gate, high voltages need be applied to the top gate. However, high voltages result in decreased reliability. It is a major objective of the invention to provide a split gate flash structure with increased floating gate charging efficiency that requires lower top gate applied voltage and thus possesses increased reliability.
Hsieh et al., U.S. Pat. No. 6,124,609, shows a split gate flash memory cell with source side injection having reduced size, partially buried source line, increased source coupling ratio, improved programmability and overall enhanced performance. U.S. Pat. No. 6,093,608 to Lin et al. shows a p-channel split gate flash memory cell with source side injection programming and tip erasing. U.S. Pat. No. 5,917,215 to Chuang et al. show stepped edge structure for an EEPROM tunneling window that eliminates the oxide thinning affect. U.S. Pat. No. 5,587,332 to Chang et al. relates to a flash EEPROM cell using polysilicon-to-polysilicon hot electron emission to erase the memory content of the cell.
It is a primary objective of the invention to provide a split gate flash structure with increased source side injection efficiency. It is another primary objective of the invention to provide a split gate flash structure that requires lower top gate applied voltage and thus possesses increased reliability. Yet another primary objective is to provide a split gate flash structure whose cell size decrease is not limited by the circuitry required to deliver the high voltage needed for traditional source side injection. It is yet another primary objective of the invention to provide a method to fabricate a split gate flash structure with increased source side injection efficiency. It is yet another primary objective of the invention to provide a method to fabricate a split gate flash structure that requires lower top gate applied voltage and thus possesses increased reliability. Yet another primary objective is to provide a method to fabricate a split gate flash structure whose cell size decrease is not limited by the circuitry required to deliver the high voltage needed for traditional source side injection.
These objectives are achieved in the invention by a split gate flash structure in which source side programming is accomplished with the heating electric field normal to the floating gate oxide barrier, and thus in the same direction as the electric field across the floating gate oxide barrier. This results in a significant increase in injection efficiency. Consequently, the top gate voltage need not be so high, which eliminates the need for special circuitry to achieve high voltage and thus facilitates decreasing the cell size. In addition, lower voltage results in improved reliability.
A new split gate structure is disclosed with improved programming efficiency. A silicon region, extending to the surface of a semiconductor substrate, has parallel source/drain regions and electrical connecting regions disposed over the source/drain region. A multiplicity of structures is situated between source drain regions. Each structure is composed of two tower structures and intervening oxide layers. A floating gate tower, in which a gate oxide layer separates a floating gate from said silicon region and an insulating layer separates said floating gate from a top gate, with a nitride layer disposed over the top gate. And a selected gate tower in which a silicon pedestal is in intimate electrical contact with said silicon region and said silicon pedestal is separated from a selected gate by an insulating layer. Along the interfacing sidewalls, the silicon pedestal is separated from the floating gate by a first intervening oxide layer and the selected gate is separated from the floating gate tower by a second intervening oxide layer.